The nXYTER Read Out Controller SysCore
Introduction
In 2007 our contribution focused the FEE (Front End Electronic), consisting of the nXYTER, an ADC (Analog Digital Converter) and the ROC (Read Out Controller).
The nXYTER is recieving analogue data directly from the sensors and detects the value and the exact time of a signal peak. It provides the time stamp digitally and the peak value analog.
For further processing the analog data has to be converted by an ADC into digital data. Since the conversion needs time, the correlation between time stamp and signal value is lost. The correlation needs to be recombined. This, the transfer of the measured data and the controlling of the functional behavior of the nXYTER and the ADC is done by our ROC Board.
Data Synchronisation
One major task of the ROC is the preparation of clock signals for the nXYTER and the ADC with well defined frequencies and phase relations to each other. This is a very sensitive point, since the ADC converts the data exactly at the rising edge of its clock and the time slot for the conversion is just about 3 ns. At the moment it is possible to change the delay at runtime from 0 ns to 31 ns (full clock cycle is 32 ns) in steps of 1 ns manually. An auto calibration function determines the right delay automatically. After the conversion, the ROC recombines the timestamps and the digitalized peak values.
Embedded Processor
The nXYTER and the ADC have user settable thresholds which can be changed using serial busses. Using our ROC, one can access these busses over Ethernet. For this the PPC is used on the ROC. The software is loaded automatically by a boot loader from a connected SD card. The content of the SD card can be changed at runtime. Hence, the software functionality of the ROC can be changed or updated remotely.
Radiation Tolerance
Most of the functionality of the ROC is realized in a Virtex4 FX20. Former measurements with FPGAs in a test beam showed that the configuration of the FPGA can change due to the beam. Hence, we developed a method to undo these unwanted changes: a radiation hard Actel CPLD takes the original bit file stored in flash memorys and refreshes the configuration of the FPGA permanently. Furthermore it is possible to change the bit file over network making it possible to change or update the hardware functionality of the ROC remotely.
MGTs
In our first test setup the FEE Board transmits the measured data via Ethernet. At the next step, we will replace this Ethernet transmission by an optical transmission using SFPs and MGTs. Furthermore, the central FPGA clock will be recovered from the optical input signals.
Want to know more?
- Get a quick overview of the SysCore Architecture
- Learn to know our DAQ chain
- Take a deeper look inside the nXYTER ROC
Want to get involved?
If you are interested into our fields of research and want to get involved, please let us know!
Related Publications
- Abel
ROC V3 - Status and next Steps
CBM Collaboration Meeting, Dresden, Germany, 2011 - Abel, Engel, Gebelein, Gottschalk, Manz, Oancea, Kebschull
Radiation Tolerance of the Universal Read Out Controller
GSI Scientific Report, Darmstadt, Gemany, 2011 - Manz, Abel, Gebelein, Kebschull
An Universal Read-Out Controller
TWEPP10, Aachen, Germany, 2010 - Abel, Manz, Kebschull
Design and Implementation of an Universal Read Out Controller
GSI Scientific Report, Darmstadt, Gemany, 2010 - Abel
Status ROC
CBM Collaboration Meeting, Split, Croatia, 2009 - Abel, Kebschull
Enhanced Design Flexibility Based on Partial Reconfiguration
CBM Collaboration Meeting, Darmstadt, Germany, 2009 - Gebelein, Abel, Kebschull
Fault-tolerant Logics for FPGA Linux
DPG conference, Bochum, Germany, 2009 - Abel, Gebelein, Kebschull
Dynamical Partial Reconfiguration for Data Acquisition
DPG conference, Bochum, Germany, 2009 - Abel, Manz, Grüll, Kebschull
Increasing Design Changeability Using Dynamical Partial Reconfiguration
RT conference, Beijing, China, 2009 - Abel, Gao, Kebschull
DPR in CBM: an Application for High Energy Physics
DATE conference, Nice, France, 2009 - Gao, Kugel, Wurz, Männer, Marcus, Abel Improved Active Buffer Board of CBM
GSI Scientific Report, Darmstadt, Gemany, 2009 - Abel, Adamczewski, Essel, Linev, Müller-Klieser, Kebschull
Software development for CBM readout controller board
GSI Progress Report, Darmstadt, Germany, 2008 - Abel
Read-out Controller (ROC): Firm/Software Aspects
CBM Collaboration Meeting, Darmstadt, Germany, 2008 - Abel, Gao, Lemke
Design and implementation of a hierarchical DAQ network
DPG conference, Darmstadt, Germany, 2008 - Abel, Schroer, Stopfkuchen, Block, Kebschull
Development of the Read Out Controller for the nXYTER Front End Board
GSI Progress Report, Darmstadt, Germany, 2007 - Abel
nNXYTER meets SysCore
CBM Collabortion Meeting, Dresden, Germany, 2007